Bus performance analysis such as transaction turn-around times and performance tuning provide useful mechanisms for debugging device drivers that initiate transactions with hardware devices via a bus. Current bus performance analysis techniques require the use of a hardware bus analyzer inserted into the bus under analysis.
Hardware bus analyzers have many shortcomings, such as cost, compatibility, scalability, and capability. For example, the cost of a typical hardware bus analyzer may exceed many thousands of dollars. When analyzing a peripheral component interconnect (PCI) bus, an industry standard architecture (ISA) hardware bus analyzer is not compatible with the PCI bus and therefore a PCI hardware bus analyzer is required. The hardware bus analyzer solution has poor scalability because it requires a one-to-one relationship between the hardware to be analyzed (i.e., the bus) and the number of hardware bus analyzers required. For example, to test a software or firmware device driver that initiates more than one transaction with more than one bus requires more than one hardware bus analyzer. Additionally, the capability of hardware bus analyzers is also a drawback. For example, the trace capability of a typical hardware bus analyzer is limited in size and functionality by the hardware bus analyzer, which typically has only one megabyte of trace capability.